1. Field of the Invention
The invention relates to an address decoding circuit and a method of address decoding, and more particularly to an address decoding circuit and a method of address decoding which are capable of identifying addresses and selecting a desired one of peripheral macros.
2. Description of the Related Art
Though peripheral macros are generally mounted on different devices, an address for practical use (hereinafter, referred to as xe2x80x9cpractical-use addressxe2x80x9d) is not always common among such peripheral macros. Accordingly, it would be necessary to identify a practical-use address, and select a peripheral macro.
FIG. 1 is a block diagram of an example of conventional address decoding circuits which select a peripheral macro through the use of a practical-use address.
The illustrated address decoding circuit is comprised only of a practical-use address decoder 2. The practical-use address decoder 2 receives an address signal 1 and transmits an address selection signal 7 to one of peripheral macros 8.
When peripheral macros were to be mounted on a chip, the address signal 1 was transmitted to the practical-use address decoder 2, an address was identified only in the practical-use address decoder 2, and a desired peripheral macro 8 was selected in accordance with the result of address identification.
When an address decoder is to be tested, test vector for a test mode is constructed in advance. A test for an address decoder is carried out through the use of the constructed test vector.
A common address decoder has been conventionally employed not only in a test mode, but also in practical use. As a result, there was a problem that test vector had to be re-constructed each time a practical-use address for individual devices is changed.
Apart from the conventional address decoding circuit illustrated in FIG. 1, Japanese Unexamined Patent Publications Nos. 61-156746 and 4-68554 have suggested address decoding circuits. However, the above-mentioned problem that test vector had to be re-constructed each time a practical-use address for individual devices is changed, remains unsolved in those address decoding circuits.
Japanese Unexamined Patent Publication No. 63-116242 has suggested a data processing apparatus including a plurality of functional blocks electrically connected in series. The suggested data processing apparatus selects one of functional blocks in accordance with a functional block selection signal.
However, since the suggested data processing apparatus includes only one address decoder, and identifies an address by means of the address decoder, the data processing apparatus is accompanied also with a problem that test vector has to be re-constructed each time a practical-use address is changed.
Japanese Unexamined Patent Publication No. 8-86836 has suggested a semiconductor integrated circuit device including first and second circuit blocks each performing certain function, a first input located between the first and second circuit blocks for receiving an output data signal from the first circuit block, a second input receiving a test data signal transmitted from outside in a test mode, an output node transmitting data signals to an input node and a test data output terminal of the second circuit block, and a selector transmitting the data signal provided to the second input in response to a test mode indicating signal, to an output.
The suggested semiconductor integrated circuit device solves the above-mentioned problem. That is, the semiconductor integrated circuit device has an advantage that it is not necessary to re-construct test vector, even if a practical-use address is changed. However, the semiconductor integrated circuit device is accompanied with another problem that since the device has to include a plurality of selectors, it would be quite difficult or almost impossible to make the device as a whole smaller in size.
Japanese Unexamined Patent Publication No. 2-154177 has suggested a module tester for testing a single chip on which a plurality of functional blocks is mounted. The tester selects a functional block to be tested in testing, and establishes a test mode in a test interface logic means equipped in the selected functional block. In response to establishment of the test mode, an interactive data bus on the chip is set on a bus interface unit by a bit. As a result, it will be necessary to re-construct a bus interface unit each time different functional blocks are to be tested.
However, in accordance with the suggested module tester, a test mode has to be established in the test interface logic means, and in addition, an interactive data bus has to be established for individual test. That is, a lot of complicated steps have to be carried out for practically performing a test in the module tester.
In view of the above-mentioned problems of the conventional address decoding circuits, it is an object of the present invention to provide an address decoding circuit which is capable of employing common test vector even if a practical-use address is changed, in the case that peripheral macros are mounted on a plurality of different chips, to thereby eliminate necessity of re-constructing test vector without having a complicated structure.
It is also an object of the present invention to provide a method of address decoding which method is capable of doing the same.
In one aspect, there is provided an address decoding circuit including (a) a first address decoder for practical use for decoding an address which is particular to an individual object, (b) a second address decoder for test use for decoding a constant address regardless of objects, and (c) a logic circuit receiving a selection signal and switching from decoding result transmitted thereto from the first address decoder to decoding result transmitted thereto from the second address decoder, and vice versa in accordance with the selection signal.
There is further provided an address decoding circuit including (a) a first address decoder receiving an address signal, comparing the thus received address signal to a certain address, and transmitting a first coincidence signal only when the address signal is coincident with the certain address, (b) a second address decoder receiving an address signal, comparing the thus received address signal to a certain address, and transmitting a second coincidence signal only when the address signal is coincident with the certain address, and (c) a selector receiving a selection signal, selecting one of the first and second coincidence signals in accordance with the received selection signal, and selecting one of a plurality of peripheral macros in accordance with the thus selected coincidence signal.
For instance, the first address decoder may be an address decoder for practical use for decoding an address which is particular to an individual object, and the second address decoder may be an address decoder for test use for decoding a constant address regardless of objects.
For instance, a binary signal having xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d is used as the selection signal.
There is still further provided an address decoding circuit including (a) a first address decoder receiving a first address signal, comparing the thus received first address signal to a certain address, and transmitting a first coincidence signal only when the first address signal is coincident with the certain address, (b) a second address decoder receiving the first address signal, comparing the thus received first address signal to a certain address, and transmitting a second coincidence signal only when the first address signal is coincident with the certain address, (c) a selector receiving a selection signal, selecting one of the first and second coincidence signals in accordance with the received selection signal, and transmitting the thus selected coincidence signal as a first address selection signal, (d) at least one third address decoder receiving a second address signal, decoding the thus received second address signal, and transmitting a second address selection signal, and (e) at least one logic circuit each receiving the first and second address selection signals, logically summing the first and second address selection signals, and selecting one of a plurality of peripheral macros in accordance with the result of logically summing the first and second address selection signals.
It is preferable that the number of the third address decoder(s) is equal to the number of register(s) equipped in each of the peripheral macros.
In another aspect, there is provided a method of address decoding, including the steps of (a) receiving an address signal, comparing the thus received address signal to a certain address, and transmitting a first coincidence signal only when the address signal is coincident with the certain address in a first address decoder, (b) receiving an address signal, comparing the thus received address signal to a certain address, and transmitting a second coincidence signal only when the address signal is coincident with the certain address in a second address decoder, (c) receiving a selection signal, and selecting one of the first and second coincidence signals in accordance with the selection signal, and (d) selecting one of a plurality of peripheral macros in accordance with the thus selected coincidence signal.
It is preferable that the steps. (a) and (b) are concurrently carried out.
There is further provided a method of address decoding, including the steps of (a) receiving a first address signal, comparing the thus received first address signal to a certain address, and transmitting a first coincidence signal only when the first address signal is coincident with the certain address in a first address decoder, (b) receiving the first address signal, comparing the thus received first address signal to a certain address, and transmitting a second coincidence signal only when the first address signal is coincident with the certain address in a second address decoder, (c) receiving a selection signal, selecting one of the first and second coincidence signals in accordance with the selection signal, and transmitting the thus selected coincidence signal as a first address selection signal, (d) receiving a second address signal, decoding the thus received second address signal, and transmitting a second address selection signal in a third address decoder, (e) logically summing the first and second address selection signals, (f) selecting one of a plurality of peripheral macros in accordance with the result of the step (e).
It is preferable that the step (d) is carried out in a plurality of the third address decoders, in which case, it is also preferable that each of a plurality of the third address decoders concurrently carried out the step (d).
It is preferable that the steps (a) and (b) are concurrently carried out.
It is also preferable that the steps (a ), (b) and (d) are concurrently carried out.
As mentioned above, the first or practical-use address decoder and the second or test-use address decoder are both employed in the present invention. The present invention makes it possible to establish test vector or test pattern through the use of a test address decoder to thereby use common test vector, even if a practical-use address is changed, in the case peripheral macros are mounted on a plurality of different chips.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.